Once fabrication of integrated circuit elements on a semiconductor substrate is completed, the semiconductor substrate is diced and packaged employing a wire bonding process. Typically, the semiconductor chip is manufactured with a passivation layer and package side bond pads, or simply “wire bond pads” on a top surface. The semiconductor chip is subsequently mounted on a chip package employing, for example, an adhesive such as an epoxy. Within the semiconductor chip, integrated circuit elements are electrically connected to the wire bond pads by interconnect structures in back-end-of line (BEOL) metallization levels. The wire bond pads are typically formed out of the last layer of metal among the back-end-of-line (BEOL) metallization levels. The wire bond pads are large enough to accommodate a ball. The wire bond pads provide structures for electrical connection between the fabricated integrated circuit elements and the chip package.
On the outside of the chip package, package pins that comprise a conductive material and arranged in a line or in a two-dimensional array are provided. Each of the package pins is electrically connected through the chip package to a package side bond pad located on the inside of the chip package. Wire bonding refers to the process of making interconnections between the wire bond pads and the package side bond pads so that the chip is electrically wired to the package pins as part of a semiconductor chip manufacturing sequence. Wire bonding is a cost-effective interconnect technology for chip packaging, and is widely practiced in the semiconductor industry.
Referring to FIG. 1, a top-down view of an exemplary prior art structure shows a semiconductor chip 10 after a wire bonding process. The exemplary prior art structure shows wire bond pads 20′ arranged in two rows along the periphery of the semiconductor chip 10. Typically, a bonding wire 30′ is connected to each of the wire bond pad 20′ via a ball bond 22′. The bonding wires 30′ typically comprise gold. The diameter of the bonding wires are from about 15 micron to several hundreds of microns. A wire bonding process employing a ball bond 22′ is called “ball bonding.” The bonding wires 30′ are welded to the ball bond 22′ by a combination of heat, pressure, and/or ultrasonic energy.
Referring to FIG. 2, a vertical cross-sectional view of another exemplary prior art structure comprises a semiconductor chip 10 mounted on a lower package housing 80 by an adhesive layer 12, which may comprise an epoxy. Package side bond pads 70 are located on the inside of the lower package housing 80, and package pins 74 are located on the outside of the lower package housing 80. Each of the package pins 74 is connected to one of the package side bond pads 70 through the lower package housing 80. One end of each of the bonding wires 30′ is connected to one of the wire bond pads 20′ through one of the ball bonds 22′ as described above. The other end of each of the bonding wires 30′ is connected to one of the package side bond pads 70 through a wedge bond 72, which tends to be larger than a ball bond 22′. The wire bonding process employing a wedge bond 72 is called “wedge bonding.” The bonding wires 30 are welded to the wedge bond 72 by a combination of heat, pressure, and/or ultrasonic energy as in ball bonding. An upper package housing 90 and the lower package housing 80 encapsulates the semiconductor chip 10 to provide protection from ambient environment and prevents oxidation or moisture ingress into the semiconductor chip 10. The chip package comprises the upper package housing 90, the lower package housing 80, the package side bond pads 70, and the package pins 74.
Many semiconductor chips have similar functionality that may be accommodated by substantially the same category of devices or circuits but require different wiring in the last interconnect level. In some other cases, a redundancy mechanism in the semiconductor chip or different portions of the semiconductor chip may be activated by altering a wiring in the last interconnect level.
In view of the above, there exists a need for capability to alter configurations of a semiconductor chip after normal manufacturing process.
While many versatile functions are provided by a semiconductor chip, the functions are limited by limitations imposed by manufacturing process. One example of such limitation is power supply network wiring in top metal wiring levels. The height of metal wires in any back-end-of-line is limited by the height of the metal line trench formed in a dielectric layer, which is typically less than 4 microns even for tallest metal lines. Further, the width of the metal wires is limited as well due to requirement for planarization. Patterning of an exposed layer of metal, while capable of providing a metal line hundreds of microns wide, tends to generate byproducts that cause contamination of the surface of the chip.
Consequently, there exists a need for a structure that may provide low resistance conduction paths for a power supply network at the top level of a semiconductor chip interconnect structures without contaminating a top surface of the semiconductor chip or with enhanced robustness in the power supply network.
Further, many radio frequency (RF) components require a large conductive structure. For example, an antenna or an inductor in a chip employing RF components may require a conductive wire on a millimeter scale. In the prior art, such structure are formed within BEOL interconnect levels, occupies a large volume, and hinders wiring of the chip as well as limited performance.
Therefore, there exists a need for alternate structures that may provide the functions of RF components without occupying much volume in BEOL interconnect levels. Furthermore, there exists a need to improve performance of RF components by lowering resistance of the RF components.
In addition, semiconductor chips generate a significant amount of heat, which tends to degrades performance of semiconductor devices, for example, by reduction of on-current, increase in resistance, etc.
Hence, there exists a need to enhance efficiency of heat transfer from a semiconductor chip to a chip package.